1. Field of the Invention
The invention relates to random access memory (RAM) integrated circuits, and more particularly to static RAM (SRAM) circuits providing a flash write or clear feature with minimum power consumption.
2. Description of the Prior Art
SRAMs hold advantages in speed and lack of power demand over comparable capacity dynamic random access memories (DRAMs). Memory cells in SRAMs are based on latches instead of capacitors as in DPJuMs. Capacitors dissipate a charge (corresponding to a bit of data) over time and thus require periodic refresh. Refresh requires power. Reading and writing to a capacitor based memory device requires both time and power. Thus, SRAMs have been advantageously used in applications requiring high speed operation (e.g. cache memory for personal computers), low power consumption (e.g. portable computers powered by batteries), or both. Complementary metal oxide semiconductors (CMOS) SRAM exhibit particularly low operating power requirements. In addition, SRAM Integrated circuits are simpler than competing dynamic RAMs because complex circuitry for clocks and refresh operations required by competing dynamic random access memories may be dispensed with. Thus SRAMs have been favored where the improved performance justifies their greater expense, or in basic electronic components where design cost to handle refresh is unjustified.
Memory cell densities achieved with DRAMs have not been matched in SRAMs and are not likely to do so in the future. An SRAM memory cell will typically include from four to six transistors, as compared to one transistor and a capacitor for a DRAM. Thus an SRkM having comparable capacity to a DRAM, when fabricated with comparable techniques, is physically larger. Large relative size compromises to some extent the advantages described above for SRAMs. As SRAMs of increased capacity have been designed they have been made physically larger. Size contributes to increased operating power requirements and reduced operating speed.
A feature of SRAM architecture are wordlines, which are used to address particular memory cells, and bit lines over which data are written and read. As SRAMs increase in size, wordlines and bit lines have become longer and more memory cells have been addressed and accessed, resulting in increased capacitance of the lines. Increased capacitance affects both for power requirements and timing, particularly for an operation called flash clear.
Flash clear (sometimes called flash write) is of particular utility in SkAMs utilized in computer cache memories. A computer cache memory duplicates selected data from main memory allowing a computer CPU faster access to that data than can be obtained from main memory, constructed from cheaper DRAMS. The protocol for selection of the data to be duplicated is critical to the effective operation of a cache. The flash clear operation can be used to clear all resident data from SRAMs of the cache, such as in tag arrays or data storage, where a selection protocol requires such an operation.
Flash clear results in relatively large currents on an SRAM. Current transients may be in the range of amperes, bordering on capacity limitations of the devices involved. In proposed SRAMs, a single wordline can have a capacitance of 230 femtofarads (fF). With 128 rows of memory cells, requiring 128 wordlines, each block has a wordline capacitance of approximately 29.5 picofarads. The device has 8 blocks so total wordline capacitance is about 240 pF. Bit line capacitance is 470 fF, for each of the two bit lines to a cell. Only one bit line, typically the bit line complement, is used for the flash clear operation. With 64 columns per block, capacitance for a block is 30 pF. Totalling capacitance over 8 blocks gives a total bit line capacitance of 240 pF.
To perform a flash clear all the wordlines are raised and the bit line complements are pulled to ground. Then, to terminate the bulk write, the bit line complements are returned to V.sub.cc and the wordlines lowered. The total amount of capacitance charged from V.sub.cc or discharged to V.sub.ss is 480 pF. Over a 10 nanosecond cycle the average current i would be: EQU i=c.DELTA.v/.DELTA.t=480 pF (5.5 v)/10 nS=264 mA.
Lengthening the cycle can reduce average current, but it must be recognized that capacitor charging and discharging is not constant. Further, lengthening flash clear cycle time is undesirable from a performance point of view. Transient currents during the flash cycle are quite large, additionally contributing to large IR (current times resistance) losses.